2+ years of experience in Physical Design for 14nm or less technology
Responsible for block level STA/timing closure / PNR.
Well versed with Synopsys Prime Time or Cadence Tempus or equivalent timing closure tool
Good communication skills English
2+ years of experience in developing and supporting design for test (DFT) structures.
Determine design for test approaches and develops DFT architecture. Design and verify DFT structures for memories (MBIST), digital and analog circuitry.
Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns.
Good communication skills English
Strong SV & UVM skills
Good knowledge in any of the protocols like Ethernet/PCIE/USB/DDR/AXI/SATA/MIPI
Experienced in developing test bench components, writing tests and coverage tuning
Digital Design and Verification Verilog/System-verilog
Good scripting knowledge using perl / python
Good communication skills English
