Design For Test (DFT)

DFT involves several key techniques to ensure the testability of integrated circuits. Key aspects include:

• Scan Insertion: Scan DRC analysis followed by scan insertion at block-level targeting simple scan and hierarchical scan approaches.
• ATPG (Automatic Test Pattern Generation): Includes ATPG DRC analysis, pattern generation for various fault models, coverage gap analysis, pattern optimization using test points and other techniques, pattern verification (both parallel and serial) using zero delay and SDF simulations along with failure debug and lastly pattern retargeting at SoC level
• MBIST (Memory Built-In Self-Test): Capability includes logical memory grouping, generation and integration of BIST controllers, verification for production and debug algorithms as well as simulation debug as required
• JTAG (Joint Test Action Group): Involves boundary scan insertion and verification.
• Timing: Generation of timing constraints for scan and memory BIST modes
• Tools Used: Tetramax, Tessent, VCS, Verdi, Simvision, DC Compiler, TEST Max, Formality, Xcelium, and Perl

Physical Design (PD)

Physical Design is the process of converting a circuit's Register Transfer Level (RTL) description into a physical layout (GDS) that can be manufactured on a silicon chip.

• RTL to GDS Flow
• Expertise on Cadence & Synopsys Toolsets
• STA & Power "expertise"

Design Verification

Design verification involves several key activities:

• Verification Plan and testplan Development
• Testcase Writing and Debugging
• Advanced Verification Techniques
• Coverage and Regression Testing
• Gate Level Simulation (GLS)
• Version Control and Bug Reporting
• Multi-core RISC V/ARM/Power PC/ATOM Processor-based Verification
• High-Speed Protocol Verification
• Formal Verification